ROM control
| SLOW_WS | Memory wait states for the slow clock domain (‘clk_slow’). The number of wait states is expressed in ‘clk_hf’ clock domain cycles. Timing paths to and from the memory have a (fixed) minimum duration that always needs to be considered/met. The ‘clk_hf’ clock domain frequency determines this field’s value such that the timing paths minimum duration is met. A table/formula will be provided for this field’s values for different ‘clk_hf’ frequencies. |
| FAST_WS | Memory wait states for the fast clock domain (‘clk_fast’). The number of wait states is expressed in ‘clk_hf’ clock domain cycles. |